Evaluation of Static Variable Ordering Heuristics for MDD Construction

After designing of Multi-Valued Logic Networks (MVLNs), the resulting circuits have to be veri ed to guarantee functional correctness. The most promising technique to cope with increasing device sizes are formal methods. Ordered Multi-Valued Decision Diagrams (OMDDs) have been proposed for formal veri cation of MVLNs. But OMDDs are very sensitive to the chosen variable ordering and several ordering heuristics have been proposed in the past. The most promising with respect to OMDD size are dynamic variable ordering techniques, but these algorithms often cannot be applied in formal veri cation approaches due to their long runtimes. Alternatively, static variable ordering heuristics have been developed that determine an ordering from the circuit topology, but these heuristics often cannot guarantee good quality. In this paper an evaluation technique is proposed that uses a pool of static variable ordering heuristics. Each heuristic is applied and the OMDD construction is started until a node or time limit is reached. Then the heuristic performed best so far is selected for the complete construction. The choice of the node and time limit allows to smoothly trade o runtime vs. quality. Experimental results are given to demonstrate the eÆciency of the approach. The technique allows to save time and memory, since only promising orders are considered.